A simplified block diagram of a conventional successive approximation analog/digital converter 1000 is shown in FIG. 1.
The successive approximation ADC 1000 includes:                an digital/analog converter 110 (hereinafter referenced as DAC);        a sample-and-hold device 150, the input of which corresponds to the successive approximation ADC 1000 input, and which is therefore supplied with the ADC 1000 input voltage, hereinafter referenced as voltage VIN, and the output of which, supplying a voltage hereinafter referenced as voltage Vin1, is connected to the input of a comparator 120 described hereinbelow. The voltage Vin1 is equal to the input voltage Vin at the end of the sampling phase (described hereinbelow). The sample-and-hold device 150 enables the input voltage Vin of the successive approximation ADC 1000 to be stabilised during the conversion phase;        a comparator 120 of which a first input 121 is supplied with the output voltage Vin1 of the sample-and-hold device 150, a second input 122 is supplied with an output voltage (analog) of the DAC 110 (hereinafter referenced as Vdac) delivered to an output 112 of the DAC 110 and an output 123 delivering an output voltage hereinafter referenced as Vcomp;        a successive approximation register 130 (SAR) of which a first input 131 is supplied with the output voltage Vcomp, a second input 132 is supplied with a voltage delivered by a conversion clock hereinafter referenced as CLK, and a set of n outputs (hereinafter referenced as a1, a2, . . . , an) 133 (n being a natural number equal to 10, for example) which supplies n inputs 111 of the DAC 110;        a circuit (optional) for storing the conversion result 140 of which a first input 141 is supplied by the output voltage Vcomp, n second inputs 142 are connected to the n outputs 133, respectively, of the register 130 and n outputs (hereinafter referenced as b1 to bn) 143 deliver the successive approximation ADC output voltage hereinafter referenced as Vout.        
A complete conversion cycle includes a sampling phase and a conversion phase. A cycle such as this requires m period(s) of the conversion clock (m being a natural number greater than or equal to one) for the sampling operation and n period(s) of the conversion clock for the analog-digital conversion operation (n being the number of bits). For example, it will hereinafter be assumed that the conversion operation is carried out on n=10 bits and that the sampling operation is carried out on 3 bits.
The conversion clock period of a conventional successive approximation ADC 1000 such as this is initially set as constant and remains so throughout the entire conversion cycle.
The choice of the conversion clock period depends on the DAC 110 set-up time and on the comparator 120 response time.
FIG. 2 shows time-dependent curves for the CLK voltages and the signals, referenced as d<9:0>, coming from the outputs b1 to bn, over one conversion phase (step 0 to step 9).
During a conversion phase 201, the output 112 of the DAC 110 generates an output voltage Vdac which, in a first conversion step, assumes a first value Vref/2 (which corresponds to a “1” on the bit of the output a1 of the SAR 130). In a second conversion step, based on the voltage at the output 123 of the comparator 120, the output a1 is maintained at “1” or reset to “0,” and the output Vdac assumes the value a1*Vref/2+Vref/4 (which corresponds to a “1) on the bit of the output a2 of the SAR 130). In a tenth conversion step, based on the voltage at the output 123 of the comparator 120, the output a9 is maintained at “1” or reset to “0,” the voltage Vdac assumes a value a1*Vref/2+a2*Vref/4+a3*Vref/8+a4*Vref/16+a5*Vref/32+a6*Vref/64+a7*Vref/128+a8*Vref/256+a9*Vref/512+Vref/1024 (which corresponds to a “1” on the bit of the output a10 of the SAR 130), Vref being a constant reference voltage. Finally, based on the voltage at the output 123 of the comparator 120, the output a10 is maintained at “1” or reset to “0”.
Hereinafter, the bit of the output a1 will be designated as the most significant bit (hereinafter designated as MSB), and the bit of the output a10 as the least significant bit (hereinafter designated as LSB).
Over the course of a conversion phase, the comparator 120 compares the output voltage Vdac to the input voltage Vin, for each of the aforesaid steps. The results of these comparisons, hereinafter referenced as b1, b2, . . . and b10, are stored in the conversion result storage circuit 140.
The clock frequency is limited both by the DAC 110 converter set-up time and by the comparator 120 response time.
For each conversion step of the conversion phase, Vdac must be established with a degree of accuracy at least equal to half the value of the least significant bit (LSB) which assumes the value Vref/1024.
FIG. 3 shows the evolution of the signal Vdac in relation to time t, in the case where Vdac assumes the value of the least significant bit (curve 301) and in the case where Vdac assumes the value of the most significant bit (curve 302).
Thus, Vdac assumes a time t1 in order to be established with a degree of accuracy at least equal to half the value of the least significant bit (LSB), and a time t2 in order to be established with a degree of accuracy at least equal to the least significant bit (LMSB). It can be noted that t1 is much less than t2.
The output voltage Vcomp of the comparator 120 can switch from 0 to 1 or from 1 to 0. The response time of the comparator 120 depends on the absolute value of the difference between the input voltage Vin of the successive approximation ADC 1000 and the output voltage Vdac of the DAC 110.
FIGS. 4 and 5, respectively, show curves of the voltages Vin, Vdac, Vcomp and CLK (in V), in relation to time (in s), in the case where the voltage Vdac is substantially equal to 0.0207 V and Vin is substantially equal to 0.380 V (FIG. 4), and in a case where the voltage Vdac is substantially equal to 0.380 V and Vin is substantially equal to 0.383 V (FIG. 5).
Thus, in the case where the voltage Vdac is substantially equal to 0.207 V and Vin is substantially equal to 0.380 V, the comparator 120 response time equals 16 ns, and in the case where the voltage Vdac is substantially equal to 0.380 V and Vin is substantially equal to 0.383 V, the comparator 120 response time equal 47 ns.
Consequently, the lower the absolute value of the difference between Vin and Vdac, the longer the comparator 120 response time.
A new value for the output voltage of the DAC 110 (corresponding to a new conversion step) is applied to the second input 122 of the comparator 120 so as to be synchronised with a current rise or fall in the clock CLK voltage, and then the value of the output voltage of the comparator 120, corresponding to the comparison of this new value for the output voltage of the ADC 110 with Vin1, is stored during the following rise or fall in the clock CLK voltage.
Thus, the minimum conversion clock period corresponds to the sum of the DAC 110 converter set-up time and the comparator 120 response time.
In a conventional successive approximation ADC, in order to ensure that the conversion clock period will be sufficiently long to be able to carry out the conversion operation with the degree of accuracy required for all of the values of the signal Vin, a clock period is generally chosen which is constant and equal to the sum of the DAC converter set-up time, in the case of the most significant bit (MSB) and the comparator response time, in the case of the slightest difference between the voltage Vin and the voltage Vdac (substantially equal to the value of the least significant bit or LSB).
In this way, one is placed in the least favourable situation in terms of the speed of the conversion operation, and, at each of the conversion steps, a loss of conversion time is thus observed for the majority of the input voltages Vin.
This loss of time is shown in relation to FIG. 6, which shows voltage curves Vin, Vdac, Vcomp and CLK (in V) in relation to time t (in μs), in a case where Vin is substantially equal to 0.7 V and where the conversion clock period is substantially equal to 0.2 μs.
A switching of the comparator 120 is observed at the moment when Vdac assumes a value of approximately 0.4 V. It can be observed that, in order for Vdac to be equal to 0.4 V, the sum of the DAC 110 converter set-up time and the comparator response time (which is of the order of 0.02 μs) is much lower than the conversion clock period. Thus, in the case of this conversion step, a time loss of substantially 0.18 μs is observed.